this document is for maintenance purposes only and is not recommended for new designs
ma9000 series 1 ds3598-3.4 the logic building block for the gps double level metal cmos/sos gate arrays is a four transistor cell-unit equivalent in size to a 2 input nand gate. back to back cell- units as illustrated, organised in rows, form the core of the array the interconnection patterns that cause groups of cell units within a row, to become defined logic cells, and the models which are used to simulate these cells, are stored as software in libraries. cells up to the complexity of, say, multiple bit shift registers are treated in this way. higher complexity functions are described by macros as the interconnection of defined cells. macros are hard, soft, or firm according to the constraints that are applied to the distribution of the component cells within the array and whether the full function is simulated by a model or by the additive effects of the component cells. features n radiation hard to 1mrad(si) n high seu immunity, latch-up free n double-level-metal cmos/sos technology n 2.5 micron design rules n typical gate delay 1.2ns with 2 loads, 60mhz toggle speeds n comprehensive library of logic cells and logic function building macros n 100% automatic place and route for typically 70% utilisation array options array cell bonding pads type units i/o power total ma9007 748 46 2 48 ma9024 2484 80 4 84 ma9040 4048 102 4 106 figure 1: cell unit silicon-on-sapphire radiation hard gate arrays ma9000 series each cell-unit is equivalent to a 2 input nand gate. any l/o site may be configured as a power pad to give flexible bonding options, but to standardise testing, preferred positions exist. may 1995
ma9000 series 2 parameter supply voltage input voltage operating temperature storage temperature min. -0.5 -0.3 -55 -65 units v v ?c ?c table 1: absolute maximum ratings stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification. is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. characterisitics & ratings symbol v dd v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 i l i oz i dd typ. 5.0 - - - - - - - - - - 0.1 max. 5.5 - 0.8 - 20 - 0.4 - 10 10 30 * units v v v %v dd %v dd v v %v dd %v dd m a m a ma conditions - - - - - i oh = -2ma i ol = 5ma i oh = -4ma i ol = 4ma - tristate output - symbol v dd v i t a t s max. 7 v dd + 0.3 125 150 parameter supply voltage ttl input high voltage ttl input low voltage cmos input high voltage cmos input low voltage ttl output high voltage ttl output low voltage cmos output high voltage cmos output low voltage input leakage current output leakage current power supply current min. 4.5 2.0 - 80 - 2.4 - 90 - - - - v dd = 5v 10%, over full operating temperature. * dependent on array type. table 2: electrical characteristics cell name nop nor2 rdt o/p edge rising falling rising falling rising ck - qb falling ck - qb data set-up time data hold time inherent delay 0.5 0.3 1.6 0.8 4.6 7.8 7.1 4.4 units ns ns ns per 1pf load* 0.4 0.2 13.6 5.0 13.7 13.6 - - table 3: electrical characteristics ac characteristics function push/pull output buffer 2 input nor reset d type * 1pf is equivalent to fanout of 5 standard gates
ma9000 series 3 propagation delay worst case maximum propagation delays for 5 volts working and 25 c are stated in the cell libraries. these are for the data change or state change which gives the greatest delay. typical process figures under the same conditions are generally 60% of those listed. use the following normalised graphs to obtain converstion factors to predict delays at any other working temperature or voltage: package options ma9040 301 x 302 x x x x x x x x x x x x ma9024 247 x 240 x x x x x x x x x x x x x x x x x ma9007 196 x 129 x x x x x x x x x x x x x dil14 dil16 dil20 dil24 dil28 dil40 dil48 dil64 lcc28 lcc40 lcc44 lcc48 lcc68 lcc84 fpk16 fpk20 fpk24 fpk28 fpk64 fpk68 fpk84 pga68 pga84 pga120 pga144 dil = dual in line lcc = leadless chip carrier fpk = leaded flatpack pga = pin grid array these are standard packages. if your package requirement is not shown above, discuss other options with an applications engineer. figure 2: propogation delay vs temperature & propogation delay vs supply voltage propagation delay factor propagation delay factor
ma9000 series 4 radiation tolerance for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. gps can provide radiation testing compliant with mil-std- 883c remote sensing method 1019 notice 5. total dose (function to specification)* 3x10 5 rad(si) transient upset (stored data loss) 5x10 10 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** <1x10 -10 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit table 4: radiation hardness parameters cell library quick guide cell name function cell units combinational gates inv inverter 1 dualinv dual inverter 1 invb fast inverter 1 invc super fast inverter 2 buff non-inverting buffer 1 buffb fast non-inverting buffer 2 buffc super fast non-inverting buffer 3 nand2 2 input nand 1 nand2b fast 2 input nand 2 nand3 3 input nand 2 nand4 4 input nand 2 nand8 8 input nand 6 nand12 12 input nand 8 nand16 16 input nand 11 and2 2 input and 2 and3 3 input and 2 and4 4 input and 3 nor2 2 input nor 1 nor2b fast 2 input nor 2 nor3 3 input nor 2 nor4 4 input nor 2 nor8 8 input nor 6 cell name function cell units nor12 12 input nor 8 nor16 16 input nor 11 or2 2 input or 2 or3 3 input or 2 or4 4 input or 3 andnor 2 + 2 input and/nor 2 andor 2 + 2 input and/or 3 ornand 2 + 2 or/nand 2 orand 2 + 2 or/and 3 a2n01 2 + 1 input and/nor 2 a201 2 + 1 input and/or 2 02na1 2 + 1 input or/nand 2 02a1 2 + 1 input or/and 2 exnor exclusive nor 3 exorn exclusive or 3 sel21nv select 1 of 2 (inverting) 3 sel2 select 1 of 2 3 sel41nv 4 bit data selector (inverting) 6 sel4 4 bit data selector 7
ma9000 series 5 cell name function cell units decoders dec2t4 2 to 4 line decoder 6 dec3t8 3 to 8 line decoder 11 dec4t16 4 to 16 line decider 40 arithmetic had half adder 5 fad full adder 8 flad fast look ahead adder 6 lah2 2 bit look ahead unit 10 lah3 3 bit look ahead unit 14 lah4 4 bit look ahead unit 24 add4 4 bit look ahead adder 50 add8 8 bit look ahead adder 106 simple latches nasr nand set reset-latch 3 nosr nor set-reset latch 3 transparent latches dl d-latch (active low) 4 dlh d-latch(actlve high) 4 sdl set d-latch 4 rdl reset d-latch 4 srdl set/reset d-latch 5 edge triggered latches rets latch with reset 7 srets latch with reset and set 8 master-slave flip-flops dt d-type 6 d2t dual input d-type 8 sdt set d-type 7 rdt reset d-type 7 srdt set/reset d-type 8 jk jk flip-flop 10 sdk jk flip-flopwith set 11 rjk jk flip-flop with reset 11 srjk jk flip-flop with reset and set 12 toggle flip-flops stt set t-type 7 rtt reset t-type 7 srtt set/reset t-type 8 synchronous counter sync synchronous counter stage 10 cell name function cell units registers / shift registers shrx multibit (x = 2-8) serial register 16-46 rshrx multibit (x = 2-8) serial reg. with reset 18-54 dregx multibit parallel register (x = 2-8) 8-22 dregtx multibit parallel register (x = 2-8) 12-36 with tri-state outputs hplsx half parallel loading shift registers 22-64 (x = 2-8) inverting tri-state buffers tribuff tristate buffer (enable high) 2 tribuffl tristate buffer (enable low) 2 trinv tristate inv buffer (enable high) 2 trinvl tristate inv. buffer (enable low) 2 input output and peripheral cells dip direct input (protection cicuit only) pup pull up (approx 30 kohms) pdo pull down (approx 40 kohms) tschmitt ttl compatible schmitt 6 cschmitt cmos compatible schmitt 6 cmosin cmos buffer (non-inverting) 1 ttlin ttl buffer (non-inverting) 3 nop push/pull output buffer (inverting) wnop multiple nop bop push/pull output buffer (non inverting) zop tri-state output buffer odn open drain output pull down odp open drain output pull up triop tristate i/o buffer 4 busint bus interface 6 stepup output buffer 6 power supply pads vdd v dd pad vss v ss pad
ma9000 series 6 macros the following macros are included in the ma9000 library. gps are constantly adding new macros to the library, please contact our nearest office for information on the latest additions. macro name acountn alu4 gcountn jcountn laddn mcompn parltyn raddn sel8 sel16 m2901 m2909 m2902 m2910 m2918 macro name asynchronous counters alu gray counters johnson counters lookahead adders magnitude comparators parity detectors ripple carry adders select 1 of 8 select 1 of 16 4 bit slice microprocessor 4 bit microprogram controller look ahead carry unit 12 bit microprogram sequencer pipeline register figure 3: development interfaces development interfaces circuit design, captive and simulation activities are carried out by the customer. schematic capture and simulation libraries for dazix and mentor graphics cae systems are provided by gps. gps will accept a simulated design and perform layout, verification checks and pg. gps will then procure masks and fabricate and test parts prior to prototype delivery. the ma9000 arrays fall within the esa capability domain. dazix is a trademark of intergraph uk mentor graphics is a trademark of mentor graphics corporation. circuit simulation input by customer post layout simulation performed by gps layout verification checks pg mask manufacture fabrication test protoype delivery circuit capture
ma9000 series 7 ordering information for details of reliability, qa/qci, test, and assembly options, see 'manufacturing capability and quality assurance standards'. s radiation hard processing r 100 krads (si) guaranteed q 300 krads (si) guaranteed h 1000 krads (si) guaranteed radiation tolerance c ceramic dil (solder seal) f flatpack (solder seal) l leadless chip carrier n naked die package type 07 ma9007 24 ma9024 40 ma9040 base type unique circuit designator qa/qci process 3sx24nnnxxxxx test process assembly process l rel 0 c rel 1 d rel 2 e rel 3/4/5/stack b class b s class s reliability level this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or serv ice. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. the se products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services prov ided subject to the company's conditions of sale, which are available on request. headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire, sn2 2qw, united kingdom. tel: (01793) 518000 fax: (01793) 518411 gec plessey semiconductors p.o. box 660017, 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 customer service centres ? france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 64 46 06 07 ? germany munich tel: (089) 3609 06-0 fax: (089) 3609 06-55 ? italy milan tel: (02) 66040867 fax: (02) 66040993 ? japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 ? north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023 ? south east asia singapore tel: (65) 3827708 fax: (65) 3828872 ? sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 ? taiwan, roc taipei tel: 886 2 5461260 fax: 886 2 7190260 ? uk, eire, denmark, finland & norway swindon, uk tel: (01793) 518527/518566 fax: (01793) 518582 these are supported by agents and distributors in major countries world-wide. ? gec plessey semiconductors 1995 publication no. ds3598-3.4 may 1995 technical documentation - not for resale. printed in united kingdom.
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